The typical memory contains an array of memory cells connected to each other by row and column lines. Each memory cell stores a single bit and is accessed by a memory address that includes a row address that indexes a row of the memory array and a column address that indexes a column of the memory array. Accordingly, each memory address points to the memory cell at the intersection of the row specified by the row address and the column specified by the column address.
In a typical computer system, the system processor communicates with the computer memory via a processor bus and a memory controller. For example, a central processing unit (CPU) issues a command and an address, which are received and translated by the memory controller. The memory controller, in turn, applies appropriate command signals and row and column addresses to the memory device. Examples of such commands include a row address strobe (RAS), column address strobe (CAS), write enable (WE), and, for some memory devices, a clock signal (CLK). In response to the commands and addresses, data is transferred between the CPU and the memory device.
The computer memory device typically includes a dynamic random access memory (DRAM) module, for example, a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). The memory module contains memory devices having one or more banks of memory chips connected in parallel such that each memory bank stores one word of data per memory address.
In an attempt to decrease memory access time, a faster form of memory, referred to as synchronous DRAM (SDRAM), was created. SDRAM transfers data with the use of a clock signal. By contrast, prior DRAM devices were asynchronous because they did not require a clock input signal for data transfer. The memory controller for synchronous devices receives the system clock signal and operates as a synchronous interface with the CPU so that data is exchanged with the CPU at appropriate edges of the clock signal.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal data banks in order to hide precharged time, and the capability to change column addresses on each clock cycle during a burst access.
As the speed of memory devices such as the SDRAM increases, (e.g., as such SDRAM devices are operated at faster clock rates) and as multiple memory banks are contemporaneously being accessed (e.g., for read, write, refreshing operations, etc.), the current demands on such systems significantly increases and can lead to over-current conditions. An over-current condition may cause electrical shorts, damage or unpredictable results in a memory device. Therefore, the current demand of a memory device needs to be better controlled.
An efficient memory current controller which facilitates the communication of the memory requests to the memory devices while limiting memory device over-current conditions is needed.